description

Technical Info
Chrome project was developed starting from Speccybob design (Thanks Mike) but while speccybob was made only with TTL chips, Chrome features 2 CPLD from Xilinx that emulates not only 48K spectrum but a more powerful 128K, 7 MHz Z80 clock and floppy disk interface. This means also a very small number of chips and a compact board too.
Every logic devices are fully reprogrammable on board enabling changes to original design in real time.

I recently reworked the entire cpld's design to match the best timing compatibility with the original 128K, some demos still runs not perfectly, but if speccybob was 99% compatible, I reached 99,9% ;)

Chrome Specification:

Cpu Zilog Z80C, Clock frequency 3.58 / 7.1 MHz
Ram memory 64K (spectrum basic), 8K Disk rom
Ram Memory 160K (paged in 16K chunks), 8K Disk ram
Sound 3 channel, 7 octave, white noise, stereo output, 1 channel internal speaker
I/O Joystick interface Kempston compatible, Expansion port, I2C interface, parallel printer out
Storage Cassette recorder, Floppy disk 800K capacity
Display Graphic 256x192 pixels resolution, 16 colors, Analog RGB Scart output

Memory Map
Chrome memory map is similar to original 128K Speccy, but add to this other two 16K pages of ram and two of rom. Memory paging is controlled by port 7FFDh and 1FFDh, you can read these ports. Notice that only Bank 2 and 5 are contended with video CPLD.

Port 7FFDh (read/write)

Bit 0-2 RAM page (0-7) to map into memory at C000h
Bit 3 Select normal (0) or shadow (1) screen to be displayed. The normal screen is in bank 5, whilst the shadow screen is in bank 7. Note that this does not affect the memory between 0x4000 and 0x7fff, which is always bank 5.
Bit 4 Low bit of ROM selection.
Bit 5 If set, memory paging will be disabled and further output to this port will be ignored until the computer is reset.
Bit 6-7 not used

Port 1FFDh (read/write)

Bit 0 If 1 maps banks 8 or 9 at 0000h (switch off rom).
Bit 1 High bit of ROM selection and bank 8 (0) or 9 (1) if bit0 = 1.
Bit 2 if 1 maps bank9 at 4000h, video page is still displayed and can be accessed at C000h.
Bit 3 Clock frequency 3.58MHz (0), 7.1MHz (1)
Bit 4 Disable (1) floppy disk memory paging
Bit 5 If set disable Chrome features ( reading/writing to port 1FFDh, reading from port 7FFDh, i2c interface. This downgrade Chrome to a simple 128K spectrum clone)
Bit 6 I2C interface - SCL signal
Bit 7 I2C interface - SDA signal

FFFFh +--------+--------+--------+--------+--------+--------+--------+--------+
      | Bank 0 | Bank 1 | Bank 2 | Bank 3 | Bank 4 | Bank 5 | Bank 6 | Bank 7 |
      |        |        |(also at|        |        |(also at|        |        |
      |        |        | 8000h) |        |        | 4000h) |        |        |
      |        |        |        |        |        | screen |        | screen |
C000h +--------+--------+--------+--------+--------+--------+--------+--------+
      | Bank 2 |        
      |        |
      |        |
      |        |
8000h +--------+--------+
      | Bank 5 | Bank 9 |
      |        |        |
      |        |        |
      | screen |        |
4000h +--------+--------+--------+--------+--------+--------+--------+
      | ROM 0  | ROM 1  | ROM 2  | ROM 3  | Bank 8 | Bank 9 | RAM +D |
      |        |        |        |        |        |        |________|2000h
      |        |        |        |        |        |        |        |
      |        |        |        |        |        |        | ROM +D | 
0000h +--------+--------+--------+--------+--------+--------+--------+

Joystick interface

The Joystick can be read from port 1Fh and is fully Kempston compatible. On idle position all bits are 0.
Bit 7 reads printer busy signal.
Port 1Fh (read only)

Bit 0 Right
Bit 1 Left
Bit 2 Down
Bit 3 Up
Bit 4 Fire
Bit 5 0
Bit 6 0
Bit 7 Printer busy

Programmable Sound Generator AY-3-8912

The AY-3-8912 works like original Spectrum 128 and is controlled by two hardware ports:
Port FFFDh (write) Register select
Port FFFDh (read) Read register
Port BFFDh (write) Write register

If you need further information about Ay registers and usage, please look at the datasheet in Download section.

Floppy Interface
The floppy disk interface is compatible with +D, originally made by Miles Gordon Technology in the late 1980s.
It controls two floppy drive double density with 800K capacity. Other +D features are a parallel printer interface and a shapshot button to transfer games snap to floppy or to make screen hardcopy.
+D contains its own memory (8K ram + 8K rom) that are paged in when the CPU fetchs an instruction at addresses 08h,66h,028Eh.
Further information on Ramsoft site

Ports used:
Port E3h (read/write) FDC status / FDC command
Port EBh (read/write) track register / track
Port F3h (read/write) sector register
Port FBh (read/write) data register
Port E7h (read) +D memory page in
Port E7h (write) +D memory page out
Port F7h (write) Printer data (8 bits)

Port EFh (Write)
Bit 0 drive select 0
Bit 1 drive select 1
Bit 2/5 not used
Bit 6 printer STROBE
Bit 7 side select

I2C Interface
This is a simple software driven I2C interface, I used it to connect a simple realtime clock based on Philips PCF8563 chip.